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MX86251 1 p/n:pm0476 rev. 1.2 , feb 11, 1998 1.introduction a graphics subsystem using the MX86251 and 3dfx in- teractive voodoo rush tm combines industry leading 3d performance with the proven performance and compat- ibility of an industry standard 2d windows accelerator. this union creates an extremely cost effective and un- compromising multimedia solution. the MX86251 pro- vides a pci system interface and high performance vga, 2d, and video features in a low cost 2d chip while the voodoo rush tm delivers 3d graphics processing power. the MX86251 connects to voodoo rush tm through the high performance 64-bit vr interface. the vr interface supports the render/refresh operation of the 2d/3d en- gines and the system control of the 3d devices. the MX86251 supports not only the basic double buffer scheme, but also triple and quad buffer swap for super smooth animation and 3d stereo glasses applications. the status signal provides 3d status to the pci host through the MX86251. the MX86251 is based on proven mx86250 2d/video window accelerator technology, while adding many en- hancements to the base functionality. all processing en- gines on the chip are running on a faster clock, up to 75 mhz which means 600 mb/sec peak memory bandwidth. higher bandwidth means higher 2d performance and higher frame rate video. the linear frame buffer write cycle from the pci bus is now executed in one clock cycle. that is, the cpu now has much greater write bandwidth into frame buffer memory. the on chip ramdac is en- hanced to 160 mhz to enable many high resolution video modes. contrast and brightness adjustments are added to the video processor so that dark mpeg-1 videos will look much better on the screen. all these features of the MX86251 combines to make a powerful graphics experience for multimedia. 1.1 features interface to 3dfx voodoo rush tm 3d graphic chipset ? provide industry leading price / performance in 2d and video ? enable the add-in of advanced 3dfx interactive voodoo rush tm 3d texture mapping and pixel rendering engines ? 4mb frame buffer enables higher resolution 3d graphics ? double, triple and quad buffer swap ? optimized lfb pci write cycles with packing fifo for most efficient usage of frame buffer bandwidth very high bandwidth, up to 600 mb/sec ? achieves single clock cycle edo dram access in graphics co-processor, video processor and display processor ? delivers 600 mb/sec bandwidth with -35 edo dram running at 75 mhz ? provides 400 mb/sec memory bandwidth using lower cost -50 edo dram chips high performance 64-bit graphics co-processor ? high performance graphics engine with 64 bit wide data path and memory data bus ? uniformly accelerated graphics operations in all pixel formats: 256 color, high color and true color ? optimized graphics engine for bitblts, rectangle fill, pattern fill, line draw, color expansion, text transfer, and clipping ? advanced 3 operand bitblt alu executes all 256 raster operations (rops) ? on chip 8x8x32 pattern memory achieves highest throughput in the most common bitblt in windows -- the pattern blt ? deep on-chip source and destination fifos for sustained burst cycles in bitblts ? double buffered co-processor registers allow concurrent processing with cpu ? built in hardware cursor ? arbitrary x-stride for efficient offscreen memory allocation motion video codec acceleration ? contrast brightness adjustment ? yuv/ycrcb conversion of industry standard yuv 4.2.2 formats ? video window zoom in both x and y direction with arbitrary ratio ? interpolation with bi-linear filters in both horizontal and vertical dimensions ? color key supports video overlay ? video window is double buffered ? video is always played in true color media port interface to mpeg decoder chips or video capture front-end ? glueless interface to vmi (video module interface)
2 MX86251 p/n:pm0476 rev. 1.2 , feb 11, 1998 connector for ? hardware mpeg-2 decoder using plug-in daughter card ? glueless interface to phillips 7110 for live video input ? interlaced video can be captured either one field only or converted to higher resolution non-interlaced frame ? built in fifo and flexible decimator high speed pci local bus interface ? support zero wait state pci burst cycles for maximum cpu write bandwidth ? single clock cycle pci write to frame buffer memory ? level command and data fifo flexible display memory configuration ? 1, 2, or 4 mb display memory ? 256k x 4, 256k x 8, and 256k x 16 dual cas or dual we dram ? fast-page and edo fully integrated for lower system cost ? integrated 24 bit true color ramdac supports 160 mhz pixel rate and 256x18 look-up table with high color and true color bypass ? dual integrated clock synthesizers ? vesa display data channel (ddc-1/2ab) protocol support ? support i 2 c channel interface ? general purpose i/o pins "green pc" power management ? support vesa dpms (display power management) standard ? built in advanced power management techniques such as internal dac power down mode and clock idle modes complete hardware compatibility ? windows 95 plug and play compliant ? vga hardware, register, and bios level 100% compatible ? pci revision 2.1 compatible
3 MX86251 p/n:pm0476 rev. 1.2 , feb 11, 1998 208pin pqfp package 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 xi xo avdd agnd scomp agnd avdd vddp vdd gnd pciclk pfxrstl pdevsels pirdyl ptrdyl pstopl pframel pa r pcbe3l gndp pcbe2l presetl pcbe1l pcbe0l pidsel pmck3dfx pfxswap vmidtackl vmihsel3 pstrobe p8 p9 gndp p10 p11 pmrql pfxgntl pfxsts poe1l pimckstrdl vmidsl vmivs vddp vmihsel0 vmihsel1 vmihsel2 vmirwl sda agnd sr sg sb 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 pcas7l pcas6l pcas5l pcas4l gndp poe0l pras1l pwe1l gnd prasb0 pweb0 vddp pma8 pma7 pma6 pma5 pma4 pma3 gnd pma2 pma1 pma0 pcas0l pcas1l pcas2l pcas3l md0 md1 md2 md3 md4 gndp md5 md6 md7 md8 md9 md10 md11 gndp md12 md13 md14 md15 md16 md17 md18 vddp md19 md20 md21 md22 avdd siref agnd svref sck pad31 pad30 pad29 pad28 pad27 vdd pad26 pad25 pad24 pad23 pad22 pad21 pad20 pad19 pad18 gndp pad17 pad16 pad15 pad14 pad13 pad12 pad11 pad10 vddp pad9 pad8 pad7 pad6 pad5 pad4 pad3 pad2 gnd pad1 pad0 romoel md31 md30 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 vsyncb hsyncl blankl tmclk tdclk penfeatl pclk gndp p7 p6 p5 p4 p3 p2 p1 p0 gndp md63 md62 md61 md60 md59 md58 md57 gnd md56 md55 md54 md53 md52 md51 md50 md49 vddp md48 md47 md46 md45 md44 md43 md42 md41 md40 gndp MX86251 md39 md38 md37 md36 md35 md34 md33 md32 md29 md28 md27 gndp md26 md25 md24 md23
4 MX86251 p/n:pm0476 rev. 1.2 , feb 11, 1998 2.functional description the MX86251 is a new generation of fully integrated graphics and video accelerator with the high performance vr interf ace to 3dfxs v oodoo rush chip set to achieve the leading-edge 3d effect. on a single chip, it integrates a 64- bit graphics coprocessor, a true-color video processor, 160mhz ramdac and dual programmable clock synthe- sizer. the MX86251 not only delivers extreme high performance in 3d/2d graphics acceleration, it also provides very rich functionality for motion video applications. the MX86251 true color video processor allows full screen full motion playback of avi and mpeg video from softw are based codecs such as mpeg, cinepak and indeo. for even higher quality mpeg video playback, the MX86251 media port supports the vmi connector linking to an external mpeg-1 decoder chip. the media port also provides for playback and capture of live video input from tv tuner or video camera. 2.1 MX86251 chip function block diagram
5 MX86251 p/n:pm0476 rev. 1.2 , feb 11, 1998 2.2 64-bit graphics co-processor the MX86251 graphics co-processor accelerates com- mon graphics user interface drawing functions , includ- ing bitblt, rectangle fill, pattern fill, bresenham line draw, and text transfer. hardware clipping and hardware cursor further reduce software driver overhead, includ- ing bitblt, rectangle fill, pattern fill, bresenham line draw, and text transfer. hardware clipping and hardware cursor further reduce software driver overhead to the minimum. the graphics co-processor supports scrardware cursor further rr further reduce software driver overhead to the minimum. the graphics co-processor supports screen widths of 640, 800, 1024, 1152, 1280, 1600 and 2048. pixel depth can be 8, 16, and 32 bits. the display memory size can be 1,2 or 4 megabytes. all co-processor drawing opera- tions are programmed with 32 bit registers in a linear address aperture. three operand bitblt the graphics co-processor executes bitblt operations between three operands: the source bitmap, the desti- nation bitmap, and the pattern bitmap. there are 256 operations on bitmaps, called raster operations (rop). an alu with three operand inputs is implemented to ex- ecute any of the 256 ro p s in a single cycle, unlike ear- lier generation gui chips which used only two operands and implemented only 16 rops. this forced the soft- ware driver to decompose those 3-operand bitblt into two or three 2-operand bitblts significantly slowing down the drawing process. source/destination fifos the three inputs to the bitblt alu are from the source fifo, the destination fifo and the pattern map buffer. the source and destination fifo are 64 bit wide and 8 levels deep. they allow the fetch cycles for source and destination pixels to be run in page mode cycles. by hav- ing destination fifo, the MX86251 can run destination read-modify-write operations in page mode reads followed by page mode writes which is substantially faster than the read-modify-write cycles in an edo-dram based system. pattern map buffer the most common bitblt operation in windows is the patblt which means painting a large window background using a brush which is an 8 by 8 pattern bitmap. many gui chips store the brush pattern bitmap in offscreen memory. during patblt, the pattern are fetched repeat- edly. to accelerate patblt, the MX86251 has on-chip memory to store a full 8 by 8 pattern bitmap. unlike others which can only store 8-bit pixels, the MX86251 can store pixel maps of 8, 16, and 32 bit pixels. this complete imple- mentation of pattern map, enables the MX86251 to ex- ecute the patblts at peak memory bandwidth using a long burst of page mode writes and thus achieving the best drawing performance. text / font drawing acceleration drawing text characters or fonts are another very com- mon windows drawing operation. the fonts are mono- chrome bitmaps that get expanded into color pixel maps in the graphics co-processor. the MX86251 optimizes this process in several ways. font bitmaps can be stored in system memory and trans- ferred to the co-processor for color expansion.the MX86251 provides a screen port to facilitate this memory to screen transfer. the screen port is mapped in a linear address aperture of 64k bytes. the monochrome font pixels are buffered in the source fifo so that concur- rent operations are enabled for font transfer from system memory and color expansion in the co-processor. the display driver can also cache font bitmaps in offscreen memory using the so called font-cache scheme. the MX86251 provides direct support of offscreen packed monochrome bitmap to color map expansion. this op- eration greatly accelerates the performance of font cache. windows 95 direct draw acceleration windows 95 direct draw is aimed to turn the windows gui environment into a game platform with high speed sprite animation. the key to sprite animation is transpar- ent blt. the MX86251 implements a flexible color key mechanism to enable high speed transparent blt. a trans- parent blt writes to screen a source bitmap, that is, a sprite, which is in an irregular shape such as a cartoon figure. the background pixels which should not be over- written are coded in the special key color. the color com-
6 MX86251 p/n:pm0476 rev. 1.2 , feb 11, 1998 pare function block in the graphics co-processor checks each pixel against the key color. if a match is found, the pixel is not written, preserving the background around the sprite. thus, an irregular shape is blted using a fast rectangle draw. in the MX86251, the color key can be in the source or the destination bitmap. transparent blt uses source color key. the destination color key can be used to protect screen areas. a mask register is defined to allow the key color be a range of color values instead of a single value. 2.3 memory controller the MX86251 memory controller module interfaces to the frame buffer dram chips which can operate in either fast page mode, or extended data out (edo) mode. the frame buffer size can be 1, 2, or 4 megabytes. industry standard 256k by 4, by 8, or by 16 dram chips are sup- ported. the memory controller performs the page mode cycle in either 2 clock cycle or 1 clock cycle, depending on the dram types being used. the highest bandwidth is delivered using -50 edo dram with 20 ns page cycle time and a 50 mhz memory clock, yielding a 400mb peak bandwidth. the MX86251 is capable of even higher memory clock speed. as faster edo dram (-35 with 15ns page mode cycle time) enters volume production, the MX86251 will deliver 533 mb/sec bandwidth which is comparable to premium priced drams such as 66 mhz sgram / sdram, or rambus rdram. the center of the memory controller is an intricate arbi- ter which receives memory access requests from the graphics co-processor for bitblt cycles, the display con- troller for screen fetch, the video processor for video play- back, the pci bus interface for cpu access, the hard- ware cursor for cursor bitmap fetch, and the dram re- fresh cycle request. the arbiter allocates memory cycles according to priority. for example, the display processor has higher priority than the graphics co-processor. a 32-level 64-bit fifo is implemented to buffer the pixels fetched from display memory for the screen refresh and video playback. the fifo entries can be flexibly allocated between three different processors: graphics, video line 1 and video line 2. this flexibility works to optimize per- formance across various screen resolutions and video playback operations. the memory controller generates all dram cycles. its logic is carefully designed to optimize dram cycle tim- ing parameters. for example, the dram entry cycle which is the time from ras precharge to the end of first cas cycle is optimized to the minimum of 4 clock cycles, ver- sus the commonly seen 5 or 6 clock cycles in other gui chips. another example is that of edo dram read cycle. the MX86251 eliminates the one extra clock cycle at the end of page mode cycles. unified memory architecture the MX86251 fully supports the vesa unified memory architecture (vuma) standard. the memory controller implements the vuma standard rq/gnt state machine which supports two request priorities. bus parking is pro- vided to minimize bus switch overhead. dram read and write operations in uma mode can have programmable number of wait states to accommodate the wide varia- tion in main system dram module access speed. in ad- dition, the dram interface drivers have programmable drive strength to work with wide range of dram inter- face loading on system motherboards. 2.4 pci bus interface unit the MX86251 bus interface unit (biu) implements a glueless connection to industry standard pci local bus which is compliant with windows 95 plugnplay require- ment. pci bus speed can be up to 33 mhz. for peak transfer rate between host cpu and the MX86251, zero wait state pci burst cycles are supported. the resultant 133 mb per second bandwidth greatly enhances the performance level of graphics intensive software such as windows gui and autocad that do lots of direct accesses to video memory. the biu has an 8 level command and data fifos to buffer host transfers and enables concurrent operations of the host cpu, the graphics engine and the video processor. the pci rev. 2.1 disconnect and retry protocol is fully supported eliminating the delays of host cpu polling for biu fifo status. 2.5 video processor the MX86251 video processor accelerates the playback of avi or mpeg video decoded by a software codec such as cinepak, indeo, or mpeg-1. profiling of the task load
7 MX86251 p/n:pm0476 rev. 1.2 , feb 11, 1998 showed that about one third time each is spent in de- compression, color conversion and pixel transfer to screen. the video processor implements the color con- version and pixel transfer in hardware, leaving only the decompression task to cpu. thus, the video play frame rate which used to be 8 to 10 fps from software codec is approximately tripled to the full motion rate of 30 fps by the MX86251. video clips are typically in qcif or cif format which are relatively small when viewed on the svga display. it is very desirable to scale up the video window to at least 640x480 or even full screen at 1024x768. the scale up can be just duplicating the pixels (zoom) which produces blocky pictures. in high end broadcast quality video pro- cessing, a smoothing filter is typically used to remove the blocky artifacts. the MX86251 video processor imple- ments both scaler and smoothing filters so that full mo- tion video can play in full screen without degradation. horizontal and vertical interpolation the video processor performs the filtering in both hori- zontal and vertical dimension. while most first genera- tion video chips only have one horizontal filter. the MX86251 provides three filters to fit the particular needs of different video decoders. the vertical interpolation fil- ter further enhances the appearance of video images by eliminating staircasing diagonal lines and illegible text commonly seen in video played by 1 st generation video chips. pixel formats the video processor supports many pixel formats. the video pixels can be in rgb formats such as krgb- 1.5.5.5, rgb-5.6.5, xrgb-8.8.8. the krgb has 1 key bit which works as a color key. more likely, the video pix- els are in yuv format such as yuv-16 (4:2:2), yuv-8 (2:1:1), or ycbcr-16 (4:2:2). the yuv format pixel has a range of value from 0 to 255, while the ycbcr format pixel values are in the range of 16 to 240. direct draw feature support the video processor fully support windows 95 direct draw with features such as chroma key, page flipping and blending. the chroma key is designed for blue screen video which is very useful in games where video sprites are employed. the new indeo 4.0 transparency feature also makes heavy use of the chroma key mechanism. the video window can be double-buffered to avoid tear- ing. the video processor executes page flipping in syn- chronization with vertical blanking. a status bit is pro- vided to inform software of the completion of page flip- ping. edge blending the MX86251 "edge blending" is an unique new feature. it is implemented to enhance the edge quality of chroma keyed video sprites. directdraw does provide api calls which support the use of edge blending. the blending feature provides 16 levels of alpha mixing of the video and graphics window. this can be used to do a very smooth dissolve or fade which are popular visual effects often used in edutainment titles. 2.6 media port the media port is a direct interface to mpeg and video decoders. a MX86251 based graphics card can deliver very extensive multimedia functionality by fully utilizing the media port. an mpeg-1 decoder chip can be incor- porated on board to deliver higher quality mpeg video. video front end such as the philips sa7110 can be built in for video capture and live tv window. the media port can accept pixel data streams from ei- ther the pixel port or the pci bus interface. the pixel data stream pass through a fifo before it gets written into the frame buffer. a flexible decimation unit can be used to reduce the input video frame size C usually required for capturing camera input. the video window for media port video stream is also double buffered for anti-tearing. interlaced video input can be captured in two ways: one field only, or converted to non-interlaced frame. vmi connector to support a wide variety of video and mpeg decoders, the media port supports the vmi ( video module inter-
8 MX86251 p/n:pm0476 rev. 1.2 , feb 11, 1998 face) standard. the vmi specifies a 40-pin connector which, in addition to the vga connector, contain an 8-bit yuv pixel bus and an 8-bit host data bus. the pixel bus transfers 8-bit packed format yuv pixels from video de- coders to the media port. the host bus transfers com- pressed mpeg data stream from the media port to the mpeg decoder chip. a small daughter card carrying the decoder chip plugs into the 40 and 26 pin connectors. to support the philips 7110 chip 16-bit yuv pixel format. the MX86251 media port has a special mode where the vmi host bus pins are used for the upper 8 bits of yuv pixels. 2.7 true color ramdac the MX86251 internal 24 bit ramdac provides three 256-entry 6-bit word color look-up table (lut) rams feed- ing three 8-bit dacs for 8-bit per pixel modes. a clock doubled mode is also provided. a 24 bit lut bypass is used in high color (15/16 bits/pixel) and true color ( 24 bits/pixel) modes. the ramdac works at pixel clock rate up to 160 mhz. many high resolution display modes are possible at this high pixel clock rate. for example, with a 2 mb card, the following video mode provides flicker free displays, 1280x1024, 256 color, @80 hz 1024x768, 64k color, @120 hz 800x600, 16m color, @120 hz 2.8 dual clock synthesizers the MX86251 contains two phase locked loop (pll) fre- quency synthesizers. they generate the dot clock (dclk) for display logic and memory clock (mclk) for memory controller and graphics engine. each pll scales the input reference frequency to a pro- grammed clock frequency. the reference frequency comes from either the crystal oscillator across the xin and xout pin or from a clock input from xin pin. the pll generate its output clock frequency based on two programmed values, the m and n value, and accord- ing to the following formula : f out = f ref * (m+2) / (n+2) * 2 r where r is the 2 bit scale value. 2.9 peripheral interface ports the MX86251 has interface ports designed to support the vesa ddc monitor interface, the i 2 c channel, and serial eeprom. vesa ddc standard the vesa ddc (display data channel) standard speci- fies a two pin serial channel between the display monitor and the graphics controller. the display monitor sends its capability and configuration datum to the graphics con- troller chip for the display driver to set up video display mode accordingly. windows 95 plug'n'play interface for display monitors is based on the ddc standard. the MX86251 provides fully compliant implementation of the ddc using the dd0 and dd1 pin. i 2 c and eeprom support the i 2 c channel is also a two pin serial bus as defined by philips. many video components such as the sa7110 video decoder relies on the i 2 c channel. the MX86251 provides the sck and sda pin for interface to i 2 c chan- nel. some graphics cards are designed to store certain card configuration or setup information in non-volatile memory storage. the MX86251 can support such a card using serial eeprom. the dd0 and dd1 pin can be pro- grammed to form an interface to serial eeprom chips. 2.10 power-on reset strapping there are 18 pins, md[17:0] reserved for strapping. these md pins have internal pull-downs. pfxswap, used for 3dfx existence detection, however, has internal pull-up. if 3dfx is connected, it will drive pfxswap low during reset time. otherwise, pfxswap will be set to 1 by the internal pull-up. the function of each power-on strap pin can also be done through i/o programming. they are defined in registers 3?5/28, 31, and 3fh. md5: reserved
9 MX86251 p/n:pm0476 rev. 1.2 , feb 11, 1998 md6: diffiden. bit 3 of register 3?5/3fh. 0--pci bus device id is read as "8626" 1--if 3dfx is detected, pci device id is read as "8627" otherwise read as"8626". md7: puma. bit 0 of register 3?5/28h. 0--puma off (default 250md) 1--puma on. issue request for md bus from 3dfx to execute rom cycle. puma on/off also can be programmed by software at 3d4/28 bit 0. md[11:10]:reserved md12: extmclk 0--use internal mclk 1--use external mclk md13: reserved md[15:14]: reserved. md20: debugmd. bit 0 of register 3?5/31h. 0--disable debug mode. 1--enable debug mode. pfxswap: en3dfx. bit 2 of register 3?5/3fh 0--3dfx connected 1--3dfx disconnected
10 MX86251 p/n:pm0476 rev. 1.2 , feb 11, 1998 2.11 pin description pci bus interface pins: pin name pin no. type description preset# 178 i this input is pci bus reset#, it is an active low signal used to initialize the gui to a known state. the trailing edge of this input loads the power on strapping inputs through md0 to md17 and pfxswap. pciclk 167 i this input is the pci bus clock. it is an 1x clock of 33mhz. frame# 173 i this input is frame#, it is low to indicate the gui that a valid address is present on the pci address bus and a new bus cycle or burst bus cycles are starting. when sampling this signal low, gui would latch the address and bus commands. irdy# 170 i this input is initiator rdy#, it is generated from an pci bus master. when it is low, irdyb indicates that the initiator is able to complete the current bus trans action if and only if the trdy# is also low. trdy# 171 sto this output is target rdy#, it is generated by gui if the current bus cycle belongs to the gui. when it is low, trdy# indicates that the gui is able to complete the current bus transaction which already targeted onto it if and only if the irdy# is also low. it remains low until this current cycle ends,then goes into high for one pci clock cycle, after that then goes into tri-state. devsel# 169 sto this output is devsel#. when driven low, it indicates that gui will respond to the current cycle. it remains low until this current cycle ends, then goes into high for one pci clock cycle, after that then goes into tri-state. stop# 172 sto this output is stop#. when driven low, it indicates that gui will request the current bus master to stop the current bus transfer. there are two configurations about this signal. one is called disconnect. under this configuration, gui will complete the current transaction as the last one. in this case, stop# will be active at the same time that trdy# is active. the other configuration is called retry. in this case, gui just request the bus master to terminate the current cycle and retry again. trdy# will not be generated in this cycle. once asserted, it remains low until this current cycle ends then goes into high for one pci clock cycle, after that then goes into tri-state. par 174 to this output is par. it is only driven during pci bus master doing read accesses from gui. when driven, it will provide an even parity across the ad[31:0], and c/be#[3:0]. this signal is an tri-state output.
11 MX86251 p/n:pm0476 rev. 1.2 , feb 11, 1998 pin name pin no. type description intr# 168 to this output is inta#. it is and interrupt request signal to system interrupt controller. this signal always hard wired to the pci bus inta# signal pin. it is an open drained output. this pin is typically unused in display subsystem design, but may be connected to irq9 via pci configuration register. idsel 181 i this input is idsel. it is used as an initialization device select during pci bus auto-configuration cycles. when high, it indicates that gui is now selected as a target for pci bus configuration cycles. cbe0# 180 i this multiplexed input is part of a pci bus commands definition or a byte enable for byte lane 0. during address phase of a pci bus transaction, it defines the command. during data phase of a pci bus transaction, it defines if byte lane 0 is engaged in the transfer or not. cbe1# 179 i this is bit 1 of bus command and byte enable. cbe2# 177 i this is bit 2 of bus command and byte enable. cbe3# 175 i this is bit 3 of bus command and byte enable. the pci bus commands supported are listed below: c\be[3:0]# pci bus command type 0000 (interrupt acknowledge) 0001 (special cycle) 0010 i/o read 0011 i/o write 0100 reserved 0101 reserved 0110 memory read 0111 memory write 1000 reserved 1001 reserved 1010 configuration read 1010 configuration write 1100 memory read multiple 1101 (dual address cycle) 1110 memory read line 1111 memory write and invalidate pci bus interface pins:(continued)
12 MX86251 p/n:pm0476 rev. 1.2 , feb 11, 1998 pin name pin no. type description ad0 41 i/o ad[31:0] is the multiplexed address and data bus for pci, which 32-bit wide. ad1 40 ad2 38 ad3 37 ad4 36 ad5 35 ad6 34 ad7 33 ad8 32 ad9 31 ad10 29 ad11 28 ad12 27 ad13 26 ad14 25 ad15 24 ad16 23 ad17 22 ad18 20 ad19 19 ad20 18 ad21 17 ad22 16 ad23 15 ad24 14 ad25 13 ad26 12 ad27 10 ad28 9 ad29 8 ad30 7 ad31 6 pci bus interface pins:(continued)
13 MX86251 p/n:pm0476 rev. 1.2 , feb 11, 1998 pin name pin no. type description ras0# 95 to this output is ras0#. it is configured in two ways. when 3dfx is not connected, it is the ras address strobe for bank 0, i.e. the first 2mb of 4mb frame buffer memory. dual cas or dual we of fast page or edo dram can be supported. when 3dfx is connected, it is the ras address strobe for the whole 4mb frame buffer. only dual cas edo dram is supported. memory access are done through puma interface. this output will be tristated if gui is not granted to access the memory bus. ras1# 98 to this output is ras1#. it is configured in two ways. when 3dfx is not connected, it is the ras address strobe for bank 1, i.e. the second 2mb of 4mb frame buffer memory. when 3dfx is connected, it is the ras address strobe for the 3dfx mmio and texture memory space, which occupies the upper 4mb above the 4mb frame buffer memory. through puma interface, this output will be tristated if gui is not granted to access the memory bus. memory refresh cycle of this bank is not generated i this case. the ras/we/oe connecctions for bank control can be outlined below: when 3dfx is not connected: content memory space ras# we# oe# frame buffer 0mb - 2mb ras0# we0# oe0# frame buffer 2mb - 4mb ras1# we1# oe0# when 3dfx is connected: content memory space ras# we# oe# frame buffer 0mb - 2mb ras0# we0# oe0# frame buffer 2mb - 4mb ras0# we1# oe1# 3dfx mmio 4mb - 6mb ras1# we0# oe0# 3dfx texture 6mb - 8mb ras1# we1# oe1# cas0# 82 to for dual cas dram type configuration, this output is cas0#. it is the cas address strobe of byte lane 0. for dual we dram type configuration, this output is we0#, it is the we# control signal of byte lane 0. in puma interface, this output will be tristated if gui is not granted to access the memory bus. dram interface pins:
14 MX86251 p/n:pm0476 rev. 1.2 , feb 11, 1998 pin name pin no. type description cas1# 81 to for dual cas dram type configuration, this output is cas1#. it is the cas address strobe of byte lane 1. for dual we dram type configuration, this output is we1#, it is the we# control signal of byte lane 1. in puma interface, this output will be tristated if gui is not granted to access the memory bus. cas2# 80 to for dual cas dram type configuration, this output is cas2#. it is the cas address strobe of byte lane 2. for dual we dram type configuration, this output is we2#, it is the we# control signal of byte lane 2. in puma interface, this output will be tristated if gui is not granted to access the memory bus. cas3# 79 to for dual cas dram type configuration, this output is cas3#. it is the cas address strobe of byte lane 3. for dual we dram type configuration, this output is we3#, it is the we# control signal of byte lane 3. in puma interface, this output will be tristated if gui is not granted to access the memory bus. cas4# 101 to for dual cas dram type configuration, this output is cas4#. it is the cas address strobe of byte lane 4. for dual we dram type configuration, this output is we4#, it is the we# control signal of byte lane 4. in puma interface, this output will be tristated if gui is not granted to access the memory bus. cas5# 102 to for dual cas dram type configuration, this output is cas5#. it is the cas address strobe of byte lane 5. for dual we dram type configuration, this output is we5#, it is the we# control signal of byte lane 5. in puma interface, this output will be tristated if gui is not granted to access the memory bus. cas6# 103 to for dual cas dram type configuration, this output is cas6#. it is the cas address strobe of byte lane 6. for dual we dram type configuration, this output is we6#, it is the we# control signal of byte lane 6. in puma interface, this output will be tristated if gui is not granted to access the memory bus. dram interface pins: (continued)
15 MX86251 p/n:pm0476 rev. 1.2 , feb 11, 1998 pin name pin no. type description cas7# 104 to for dual cas dram type configuration, this output is cas7#. it is the cas address strobe of byte lane 7. for dual we dram type configuration, this output is we7#, it is the we# control signal of byte lane 7. in puma interface, this output will be tristated if gui is not granted to access the memory bus. we0# 94 to for dual cas dram type configuration, this output is we0#. it is the we# control signal of bank 0. for dual we dram type configuration, this output is cas0#, it is the cas address strobe of bank 0. in puma interface, this output will be tristated if gui is not granted to access the memory bus. we1# 97 to for dual cas dram type configuration, this output is we1#. it is the we# control signal of bank 1. for dual we dram type configuration, this output is cas1#, it is the cas address strobe of bank 1. in puma interface, this output will be tristated if gui is not granted to access the memory bus. if gui is granted, this has the above function when ma9outse is 1. if ma9outse is 0, it is the ma9, which is necessary for asymmetrical dram. oe# 99 to this output is oe#. it is the oe# control signal for both banks of frame buffer memory when 3dfx is not connected. it controls access of the lower 2mb of frame buffer or 3dfx mmio otherwise. in puma interface, this output will be tristated if gui is not granted to access the memory bus. ma0 83 to the outputs ma[8:0] is the dram memory address bus for both banks. ma1 84 it is used to pass the ras address and cas address to drams. ma2 85 in puma interface, these outputs will be tristated if gui is not granted to access ma3 87 the memory bus. ma4 88 ma5 89 ma6 90 ma7 91 ma8 92 dram interface pins: (continued)
16 MX86251 p/n:pm0476 rev. 1.2 , feb 11, 1998 pin name pin no. type description md0 78 i/o md[7:0] is the dram data bus of memory plane 0 of bank 0 or bank 1. md1 77 in bios rom accesses, these are the data inputs[7:0] of external rom. md2 76 they are also served as power-on strapping inputs. md3 75 md4 74 md5 72 md6 71 md7 70 md8 69 i/o md[15:8] is the dram data bus of memory plane 1 of bank 0 or bank 1. md9 68 they are also served as power-on strapping inputs. md10 67 md11 66 md12 64 md13 63 md14 62 md15 61 md16 60 i/o md[23:16] is the dram data bus of memory plane 2 of bank 0 or bank 1. md17 59 md[17:16] are also used as power-on strapping inputs. md18 58 md19 56 md20 55 md21 54 md22 53 md23 52 md24 51 i/o md[31:24] is the dram data bus of memory plane 3 of bank 0 or bank 1.in md25 50 bios rom accesses, md[31:16] are the address outputs[15:0] for e xternal rom. md26 49 md27 47 md28 46 md29 45 md30 44 md31 43 dram interface pins: (continued)
17 MX86251 p/n:pm0476 rev. 1.2 , feb 11, 1998 pin name pin no. type description md32 105 i/o md[39:32] is the dram data bus of memory plane 4 of bank 0 or bank 1. md33 106 md34 107 md35 108 md36 109 md37 110 md38 111 md39 112 md40 114 i/o md[47:40] is the dram data bus of memory plane 5 of bank 0 or bank 1. md41 115 md42 116 md43 117 md44 118 md45 119 md46 120 md47 121 md48 122 i/o md[55:48] is the dram data bus of memory plane 6 of bank 0 or bank 1. md49 124 md50 125 md51 126 md52 127 md53 128 md54 129 md55 130 md56 131 i/o md[63:56] is the dram data bus of memory plane 7 of bank 0 or bank 1. md57 133 md58 134 md59 135 md60 136 md61 137 md62 138 md63 139 dram interface pins: (continued) uma interface pins: pin name pin no. type description smurq# 182 o this is the mreq# signal for vesa uma interface. gui uses this signal to request memory accesses on uma. smgnt# 183 i this is the mgnt# signal from vesa uma interface. gui will drive dram interface signals when this signal is active in uma configuration.
18 MX86251 p/n:pm0476 rev. 1.2 , feb 11, 1998 rom bios interface pins: pin name pin no. type description romoe# 42 o this output is romoe#. it may be connected to either one or both of the bios rom chip select and output enable pins directly. internal vcg related interface pins: pin name pin no. type description xi 157 i this input is used as a reference frequency input for internally imple mented oscillator. an external crystal or oscillator of 14.318mhz may be used. if an external crystal is used, it must be connected between xin and xout. if an external oscillator is used, it must connect to xin. in this case, the xout must be left open. xo 158 o this is used as a reference frequency output for internally implemented oscillator. if an external crystal is used, it must be connected between xin and xout. if an external oscillator is used, the xout must be left open. internal ramdac related interface pins: pin name pin no. type description svref 4 i this pin is the voltage reference of 1.2v for internal dac and monitor sence logic. it must be connected with a 0.1u capacitor to avcc of ramdac. scomp 161 i this pin is the compensation input for internal dac. it must be connected with a 0.1u capacitor to avcc of ramdac. siref 2 i this pin is the current reference. sr 206 o this pin is the analog output of the pixel color red component to monitor. it has a voltage level of 0.0v(blank) to 0.7v(full scale) when terminated with 75 ohm double loads. sg 207 o this pin is the analog output of the pixel color green component to monitor. it has a voltage level of 0.0v(blank) to 0.7v(full scale) when terminated with 75 ohm double loads. sb 208 o this pin is the analog output of the pixel color blue component to monitor. it has a voltage level of 0.0v(blank) to 0.7v(full scale) when terminated with 75 ohm double loads.
19 MX86251 p/n:pm0476 rev. 1.2 , feb 11, 1998 3dfx related interface pins: pin name pin no. type description prxrst# 168 o this is the hardware reset signal for 3cfx interface. it is connected directly to hreset# input of 3dfx reset will be reflected on this pin. software reset pin sreset# of 3dfx can be tighten to vdd. pmck3dfx 182 o this is the puma clock for 3dfx interface. gui sends this signal to the input clock pin of 3dfx. pfxswap 183 i this is the swap request from 3dfx. gui is notified by it to swap crt or vp double buffers. it is also used to detect 3dfx's existence during power-on reset. when receiving low, it means 3dfx is connected. otherwise, 3dfx is not connected. pmrq# 192 io this is a multi-function pin. if vmi is used, it is used as bit 4 of the host data bus, which is bidirectional. it is an output pin for pixel data 12 (p12) if pixtest is on. otherwise, its used as an output pin of the puma request for 3dfx interface. gui uses this signal to request memory accesses through puma. pfxgnt# 193 io this is a multi-function pin. if vmi is used, it is bit 5 of the host data bus. it is an output pin for pixel data 13 (p13) if pixtest is on. otherwise, it's used as an input pin of the puma grant for 3dfx interface. gui will drive dram interface signals when this signal is active. pfxsts 194 io this is a multi-function pin. if vmi is used, it is bit 6 of the host data bus. it is an output pin for pixel data 14 (p14) if pixtest is on. otherwise, it's used as an input of the serial status from 3dfx. gui will accumulate it to a 16 bit mmio register. poe1# 195 io this is a multi-function pin. if vmi is used, it is bit 7 of the host data bus. it is an output pin for pixel data 15 (p15) if pixtest is on. otherwise, it's used as the output pin oe#1, which is the oe# control signal for high bank of dram.
20 MX86251 p/n:pm0476 rev. 1.2 , feb 11, 1998 media port and feature connector related interface pins: pin name pin no. type description p0 141 io p[7:0] is the pixel or video data bus from/to external feature connector or video p1 142 module interfaces. p2 143 for 8-bit feature connector, this is a bi-directional pixel data bus. when p3 144 penfeatl is low, it functions as inputs. the pixel data from external display or p4 145 video card will be passed to the internal ramdac for display. if penfeatl p5 146 is high, the internal ramdac uses pixel data internally generated for display. p6 147 in this case, if pa output control for dpms, which is defined in bit 3 of register p7 148 3?5/26, is set to normal operation, gui will drive out pixel data. otherwise, it will tristate the output. if vmi is used, p[7:0] is the video data inputs. this chip supports saa7110 video decoder and cl480 mpeg decoder interfaces. for saa7110 interfaces, p[7:0] is the lower byte of the 16-bit video data inputs. for cl480 interfaces, its the 8-bit video data inputs. p8 187 io p[15:8] is the pixel data bus from/to external feature connector or host data p9 188 io bus from/to vmi. p10 190 io if vmi is used, p(15:8) is used as the host data bus, which is bi-directional. p11 191 io through this bus, cpu can access the vmi module. for saa7110 interfaces, p(15:8) is the higher byte of the 16-bit video data inputs. for cl480, its the 8-bit host data bus, which is inputs in read cycles, and outputs in write cycles. otherwise, p(15:8) functions as pixel output or video input. when penfeatl is low, it is used for video input, which will be passed to the internal ramdac for display . if penfeatl is high, the internally generated pixel data will be driven out to video card if pa output control for dpms is set to normal operation. pclk 150 io this is the pixel clock input/output pin. for 8-bit feature connector, it's an input when penfeatl# is low. in this case, it is used for internal ramdac display. when penfeatl# is high, the internally generated pixel clock is driven out through this pin. for vmi connection, pclk is always put in tri-state. ramdac use internal pixel clock for display. if external dclk is used, only 8-bit feature connector configuration is allowed, i.e. other video interfaces are not applicable. penfeat# 151 i this is the evideo# pin used as bidirection control for 8-bit feature connector. when set to 1, gui will drive p[15:0], blank#, hsync, vsync and pclk to the feature connector. when set to 0, all of these signal pins are tri-stated. if video interface is enabled, i.e. either saa7110 or cl480 is used for video data input, this pin loses its function.
21 MX86251 p/n:pm0476 rev. 1.2 , feb 11, 1998 pin name pin no. type description tdclk 152 i it is a dual-function pin. if external vcg is selected, it is used as dclk input. otherwise, it is the video input pin for video interface. tmclk 153 i it is a dual-function pin. if external vcg is selected, it is used as mclk input. otherwise, it is the cflevel input from cl480 or odd from saa7110. when used as the cflevel from cl480, it indicates that the cl480 coded data fifo for compressed data is going to be exhausted. gui will generate the interrupt signal to inform the software to put more compressed data into cl480. when used as the odd signal from saa7110, it is an odd/even field indication for interlaced video. when high, it is odd field, otherwise, even field. gui uses this to determine the memory location for incoming video data. blank# 154 io this is a multi-function pin. for 8-bit feature connector, when penfeatl# is high, the internal blank# signal is output to control ramdac display. when penfea tl# is set to 0, its an input from feature connector. gui uses it to control ramdac display. for vmi or saa7110, it's the href input. and for cl480 it's the hsync# input. in either case, it indicates that video data of a scanline is coming in. hsync# 155 to it's the hsync# output pin, which is the horizontal sync to analog monitor. for 8-bit feature connector, it is enabled when penfeatl# is high or either saa7110 or cl480 is selected. otherwise, it is tristated. vsync# 156 to i t s the hsync# output pin, which is the horizontal sync to analog monitor. for 8-bit feature connector, it is enabled when penfeatl# is high or either saa7110 or cl480 is selected. otherwise, it is tristated. vmivs 198 io if external vcg is selected, this pin is used as one of the mclk select output, mcsel1. mcsel[2:0] is used to select mclk frequency from external vcg. if internal vcg is used, it is an input pin for video interface. it's the vref for vmi, vs for saa7110 and vsync# for cl480. either one indicates that it's the frame start of input video data. sck 5 io it's the i 2 cclk input/output pin for both saa7110 interface or ddc2 monitor control. as an input, the i 2 c clk value can be monitored by reading bit 2 of the memory-mapped register port at offset 31c or bit 2 of the i/o register at 3?5/50. to generate clock pulses, software can just program either bit 0 of the above memory-mapped register or bit 5 of the io register at 3c4/1e. if 0 is programmed, this pin is pulled low. if 1 is programmed, this pin is tri-stated. with the external pull-up, it makes i 2 cclk go to high state. in this way, clock pulses are generated. media port and feature connector related interface pins:(continued)
22 MX86251 p/n:pm0476 rev. 1.2 , feb 11, 1998 pin name pin no. type description sda 204 io this is a multi-function pin. if external vcg is selected, this pin is used as of the mclk select output, mcsel2. otherwise, it is the serial data input/ouput pin for i 2 c bus. as an input, it can be monitored by reading bit 3 of the memory-mapped register at offset 31c, or of the i/o port at 3?5/50. to generate data, software can program either bit 1 of the above memory-mapped register or bit 6 of the i/o register at 3c4/1e. vmihsel0 200 o this is a dual-function pin. if external dclk is selected, this pin is used as one of the dclk select output, vcksel0. vcksel[3:0] is used to select dclk frequency from external vcg. otherwise, it is used as ha0 for vmi or hsel0 for cl480. ha[3:0] and hsel[3:0] are the host address bus for vmi and cl480 individually. vmisel1 202 o this is a dual-function pin. if external dclk is selected, this pin is used as one of the dclk select output, vcksel1. otherwise, it is used as ha1 for vmi or hsel1 for cl480. vmisel2 202 o this is a dual-function pin. if external dclk is selected, this pin is used as one of the dclk select output, vcksel2. otherwise, it is used as ha2 for vmi or hsel2 for cl480. vmisel3 202 o this is a dual-function pin. if cl480 or vmi interface is enabled, it is ha3 or hsel3 output, the address for host i/o accesses. it is also a general data input / output pin. as an input, it can be read through bit 1 of io port 3?5/50. otherwise, it is driven out as an general data output. bit 4 of register 3c5/1e is selected as its output value. vmirw# 203 io this is a dual-function pin. if external dclk is selected, this pin is used as one of the dclk select output, vcksel3. otherwise, it is used as r/w# for vmi or cl480. in that case, it controls the host read/write with them. for read cycles, it is driven high, for write cycles, it is driven low. vmids# 197 o it is a dual-function pin. if external vcg is selected, it is used as one of the mclk select output, mcsel0. otherwise, it is used as ds# for vmi or cl480. gui pulls it low to select vmi target or cl480 for read/write operation. media port and feature connector related interface pins:(continued)
23 MX86251 p/n:pm0476 rev. 1.2 , feb 11, 1998 pin name pin no. type description vmidtack# 184 io it is a dual-function pin. if cl480 or vmi interface is enabled, it is the dtack# input, which is the host data acknowledge from them. when set to 0, it indicates that cl480 or vmi target is ready for data receiving or output. gui can thus complete the cycle. if not the above case, it is a general data i/o pin. it can be read through bit 0 of io port 3?5/50. as an output, itin tr istate normally. write to i/o register 3c2, 3c5/1d or 3c5/1e will enable it. bit 3 of 3c5/1e is selected as its output value. pstrobe 186 o this is the data write strobe for external devices when vmihsel3 or vmidtackb is used as general data input/output pins. it is used to latch vmihsel3 and vmidtackb driven by gui. it is high when i/o registers 3c2, 3c5/1d or 3c5/1e is written or power-on reset completes. if external vcg is used, it is used to latch vcksel[3:0]. the external vcg will use these values to generate expected frequencies of dclk. pimckstrd#196 o this is the data read enable for external devices when vmihsel3 or vmidtackb is used as general data input/output pins. the external devices should drive vmihsel3 and vmidtackb when this signal is low. otherwise, put them to tri-state. media port and feature connector related interface pins:(continued) power pins: pin name pin type pin no. drive(ma) c_load(pf) vddp - 11,57,123,164,199, - - gndp - 21,48,65,73,100,113, - - 140,149,176, 189 vdd - 30,93,165, gnd - 39,86,96,132,166, - - avdd - 1,159, 163 avss - 3,160, 162,205
24 MX86251 p/n:pm0476 rev. 1.2 , feb 11, 1998 4.0 electrical characteristics 4.1 absolute maximum ratings ratong value dc supply voltage (vcc) 4.75v to 5.25v dc input/output voltage (vin/vout) -0.5v to vcc+0.5v ambient temperature (ta) 0 to 70 celsius storage temperature (tstg) -40 to 125 celsius esd rating (rzap=1.5k, czap=100pf) 2000v power dissipation (pd) 1.75w table 4-1 absolute maximum ratings 4.2 dc characteristics symbol description min max test conditions vil input low voltage - 0.8v vih inout high voltage 2.4v - vol output low voltage - vss+0.4v i=2/4/8/24 ma voh output high voltage 2.4v - i=-2/-4/-8/-10 ma icc power supply current - 350ma vcc=5v, 1024x768x256cx75hz iil input low current -10ua 10ua vcc=5.25v, vin=0v iih input high current - 10ua vin=vcc idd static idd current - 600ua ioz output tri-state leakage current -10ua 10ua cin input capacitance - 10pf cout output capacitance - 10pf table 4-2 dc characteristics of MX86251
25 MX86251 p/n:pm0476 rev. 1.2 , feb 11, 1998 4.3 ac characteristics 4.3.1 clock timing symbol parameter min max units tmcyc mclk period 14 - ns tmlo mclk low time 7 - ns tmhi mclk 7 - ns table 4-3 mclk timings symbol parameter min max units tdcyc dclk period 6.67 - ns tdlo dclk low time 3.34 - ns tdhi dclk high time 3.34 - ns table 4-4. dclk timings mclk tmlo tmhi tmcyc dclk tdlo tdhi tdcyc figure 4-1. clock timing diagram
26 MX86251 p/n:pm0476 rev. 1.2 , feb 11, 1998 4.3.2 reset timings symbol parameter min max units trst reset# pulse width 150 - ns trstdsu power-on strap data setup time 15 - ns trstdh power-on strap data hold time 10 - ns table 4-5. reset timings md trstdsu trst reset# trstdh fi g ure 4-2. reset timin g dia g ram
27 MX86251 p/n:pm0476 rev. 1.2 , feb 11, 1998 4.3.3 pci interface timing 4.3.3.1 pci write timings symbol parameter min max units tsu input setup time from clk 7 - ns th input hold time from clk 0 - ns tval output valid time to pciclk - 12 ns toff clk to tri-state delay 2 - ns table 4-6. pci write timings ad[31:0] adr data 0 data 1 th tsu tsu mclk frame# th tsu irdy# th c/be[3:0] command be 0 be 1 th tsu trdy# tval toff desel# fi g ure 4-3. pci write timin g dia g ram
28 MX86251 p/n:pm0476 rev. 1.2 , feb 11, 1998 4.3.3.2 pci read timings symbol parameter min max units ton ad output active from float 2 - ns tdoff ad output float from clk delay 2 - ns toff clk to tri-state delay 2 - ns table 4-7. pci read timings ad[31:0] adr data 0 tsu pciclk frame# irdy# c/be[3:0] command be 0 ton trdy# tdoff toff devel# fi g ure 4-4. pci read timin g dia g ram
29 MX86251 p/n:pm0476 rev. 1.2 , feb 11, 1998 4.3.3.3 pci disconnect timings ad[31:0] adr data 0 pciclk frame# irdy# c/be[3:0] command be 0 trdy# tval stop# fi g ure 4-5. pci disconnect timin g dia g ram devsel# toff
30 MX86251 p/n:pm0476 rev. 1.2 , feb 11, 1998 4.3.4 dram timings symbol parameter min max units notes trp ras# precharge time 2 4.5 mclk 1 trcd ras# to cas# delay time 1.5 5 mclk 1 tasr row address setup time 4 - ns 2,3 trah row address hold time 15 - ns tcas cas# pulse width 7 - ns 2,4 tcp cas# precharge time 7 - ns 2 twcs we# to cas# setup time 5 - ns 2,4,5 toes oe# low to cas# high setup time 5 - ns 2,4,7 tasc column address setup time 7 - ns 2,3,4 tcah column address hold time 6 - ns 2,3,4 tds write data to cas# setup time 4 - ns 2,4,6 tdh write data hold time 5 - ns 2,4,6 tcac read data access time from cas# - 10 ns tcoh raed data hold time after cas# low 3 - ns table 4-8. edo dram timings trp mclk ras# cas# ma[8:0] md[63:0] wa0 wa1 we# oe# tdh trcd rowa trah tcas dummy (note) tcp tasc tcah wa2 ra0 ra1 ra2 rowa tasr wd0 wd1 wd2 rd0 rd1 rd2 twcs tds tcoh tcac toes note:read dummy cycle is optional. fi g ure 4-6. edo dram read/erite timin g s
31 MX86251 p/n:pm0476 rev. 1.2 , feb 11, 1998 notes: 1.trp and trcd can be programmed through crtc register 1ah. 2.mclk period=15ns, i.e. 65mhz. 3.test under ma loading 30pf. 4.test under cas# loading 15pf. 5.test under we# loading 20pf. 6.test under md loading 15pf. 7.test under oe# loading 20pf. 4.4 esd protection capability - mil mode : 1500v - eiaj mode : 300v
m acronix i nternational c o., l td. headquarters: tel:+886-3-578-8888 fax:+886-3-578-8887 europe office: tel:+32-2-456-8020 fax:+32-2-456-8021 japan office: tel:+81-44-246-9100 fax:+81-44-246-9105 singapore office: tel:+65-747-2309 fax:+65-748-4090 taipei office: tel:+886-3-509-3300 fax:+886-3-509-2200 m acronix a merica, i nc. tel:+1-408-453-8088 fax:+1-408-453-8488 chhicago office: tel:+1-847-963-1900 fax:+1-847-963-1909 http : //www.macronix.com macronix international co., ltd. reserves the rignt to change product and specifications without notice. MX86251 32

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